Diversification properties of investments in shipping
MB Grelck, S Prigge, L Tegtmeier… - The Journal of …, 2009 - jai.pm-research.com
In contrast to the more established alternative asset classes like real estate or hedge funds,
there is not much research available for investments in shipping. This article contributes to …
there is not much research available for investments in shipping. This article contributes to …
Investing in times of inflation fears: Diversification properties of investments in liquid real assets
MB Grelck, S Prigge, L Tegtmeier, M Topalov, I Torpan - 2010 - econstor.eu
The financial crisis and the rescue measures taken by governments and central banks
increased investors' interest in liquidity and in real assets supposed to offer a hedge against …
increased investors' interest in liquidity and in real assets supposed to offer a hedge against …
[HTML][HTML] Efficient memory copy operations on the 48-core intel scc processor
… MB/s for the L1 cache for size 8-16KB, 285 MB/s for reading the L2 cache at size 32256KB
and 107 MB/s … Writes to the L2 cache perform at 116 MB/s, or 130 MB/s when using the write-…
and 107 MB/s … Writes to the L2 cache perform at 116 MB/s, or 130 MB/s when using the write-…
Parallel processing of image segmentation data using Hadoop
… This section will analyze the CPU cores usage distribution for 250 MB, 300 MB, 350 MB,
400 MB, 450 MB and 500 MB image datasets. At first the CPU cores usage distribution for the …
400 MB, 450 MB and 500 MB image datasets. At first the CPU cores usage distribution for the …
SaC/C formulations of the all‐pairs N‐body problem and their performance on SMPs and GPGPUs
…, R Bernecky, R Douma, C Grelck - Concurrency and …, 2014 - Wiley Online Library
… The system is clocked at 2.8 GHz and comes with 64 KB L1 cache and an 8 MB L2 cache.
It … Each processor has a 4 MB eight-banked 16-way associative L3 cache shared across all …
It … Each processor has a 4 MB eight-banked 16-way associative L3 cache shared across all …
[PDF][PDF] Efficient heap management for declarative data parallel programming on multicores
… Rather than complex structures of relatively small items interconnected by references, we
are faced with large chunks of memory, usually arrays, which often account for 100s of MB each…
are faced with large chunks of memory, usually arrays, which often account for 100s of MB each…
[HTML][HTML] On mapping distributed s-net to the 48-core intel SCC processor
… write at a speed of up to 20 MB/s, cache hits write at up to 125 MB/s. For reading the speed
… and L2 cache misses read at up to 20 MB/s whereas cache hits read at up to 285 MB/s. …
… and L2 cache misses read at up to 20 MB/s whereas cache hits read at up to 285 MB/s. …
Combining high productivity and high performance in image processing using Single Assignment C on multi-core CPUs and many-core GPUs
We address the challenge of parallelization development of industrial high-performance
inspection systems comparing a conventional parallelization approach versus an auto-…
inspection systems comparing a conventional parallelization approach versus an auto-…
Programming languages for data-intensive HPC applications: A systematic mapping study
A major challenge in modelling and simulation is the need to combine expertise in both
software technologies and a given scientific domain. When High-Performance Computing (HPC) …
software technologies and a given scientific domain. When High-Performance Computing (HPC) …
Engineering concurrent software guided by statistical performance analysis
This paper introduces the ADVANCE approach to engineering concurrent systems using a
new component-based approach. A cost-directed tool-chain maps concurrent programs onto …
new component-based approach. A cost-directed tool-chain maps concurrent programs onto …